1. Field of the Invention
The invention relates to an isolation structure of a trench capacitor and a fabricating method thereof, and more particularly, to an isolation structure of a trench capacitor and a fabricating method thereof applying to dynamic random access memories (DRAMs).
2. Description of the Prior Art
With the development of electrical products, integrated circuits and electrical products have been pushed for size reductions to match the trend of high integration and high density. As a result, trench capacitors have become main structures of DRAM products. The fabrication of trench capacitors comprises forming a plurality of deep trenches in a substrate, forming capacitors in the deep trenches, and electrically connecting the trench capacitors with transistors so as to reduce the area of each memory cell.
Please refer to FIG. 1. FIG. 1 is a section view of two adjacent trench capacitors according to the prior art. The substrate 10 comprises two adjacent trench capacitors 12, 14 disposed in the deep trenches 16, 18 respectively. The trench capacitor 12 comprises a storage node 24, capacitor dielectric layer 26, and a N+ buried plate 28. The trench capacitor 12 usually further comprises a buried strap 20 disposed on the storage node 24 and contacting the storage node 24. The buried strap 20 is used for electrically connecting the trench capacitor 12 and an adjacent active area (AA). A collar oxide layer 22 is disposed on the surface of the deep trench 16 for isolating the storage node 24 and the substrate 10. Furthermore, a shallow trench isolation (STI) 30 is disposed between the trench capacitors 12, 14 for isolating the trench capacitors 12, 14. As shown in FIG. 1, the STI 30 straddles on the two deep trenches 16, 18 and overlaps a portion of the collar oxide layer 22 and the storage node 24 of the deep trenches 16, 18.
Please refer to FIG. 2 to FIG. 3. FIG. 2 to FIG. 3 are schematic diagrams of the fabrication of the STI 30 of the trench capacitors 12, 14 shown in FIG. 1. First, a doped silicate glass layer 34 is deposited on the substrate 10 comprising the trench capacitors 12, 14, wherein the substrate 10 already has a pad layer 32 thereon. The doped silicate glass layer 34 covers the pad layer 32 and fills the recesses 16a, 18a of the deep trenches 16, 18. Then, an anti-reflection coating (ARC) layer 36 is deposited on the doped silicate glass layer 34, and a photoresist layer 38 is coated on the ARC layer 36. After that, a lithography process is performed to pattern the photoresist layer 38 so as to form an opening 40 defining a shallow trench.
As shown in FIG.3, a plasma-dry-etching process is performed by taking the photoresist layer 38 as a hard mask. Therefore the ARC layer 36, the doped silicate glass layer 34, the pad layer 32, the substrate 10, and a portion of the buried strap 20, the storage node 24, and the collar oxide layer 22 are removed through the opening 40, so that a shallow french 42 is formed. Then, the photoresist layer 38, the residual ARC layer 36, and the residual doped silicate glass layer 34 are removed. Finally, the shallow trench 42 and the top recesses of the deep trench 16, 18 are filled with isolation materials, and the isolation materials are planerized to complete the fabrication of the STI 30 of the trench capacitors according to the prior art.
However, for this prior-art method, when the photoresist layer 38 is used to define the shallow trench 42 for directly fabricating the STI 30, the photomask for defining the active area is susceptible to misalignment so that the STI 30 shifts to one of the deep trenches 16, 18. As shown in FIG.4, the STI 30 leans toward the deep trench 16. In this situation, a serious defect may occur for the left trench capacitor 12. This is because the contact area of the storage node 24 and the buried strap 20 is reduced resulting in the resistance of the trench capacitor 12 being raised. Even more, the buried strap 20 may fail to contact the storage node 24 so as to cause a broken circuit. Consequently, the french capacitor 12 cannot work.
Since the resistances of the trench capacitors 12 and 14, influenced by the overlapping region of the active area and the trench capacitor 12 and the contact area of the buried strap 20 and storage node 24, are one of the key factors affecting the DRAM performance, the area of the storage node 24 surrounded by the collar oxide layer 22 should be larger when fabricating the trench capacitor 12. Referring to FIG. 1, a parameter “X” is defined, wherein the parameter “X” stands for the maximum distance in the overlapping region between the active area and the trench capacitor 12 in the x-direction. For reducing the resistance, the maximum “X” has to be as large as possible. Therefore the area of the deep trench 16 that the shallow trench 42 occupies should be as small as possible. However, according to the fabrication process of the STI 30 in the prior art, this may cause misalignment resulting in electrical leakage. As a result, the prior-art STI and fabrication method thereof needs to be improved for raising the process yield.